1. Field of the Invention
The present invention relates to a DLL (Delay Locked Loop) circuit for adjusting the delay amount on the basis of the phase comparison result between an internal supply clock and a reference clock to synchronize the internal supply clock with the reference clock.
2. Description of the Prior Art
Recent, increase in circuit scale of integrated circuits have caused delay of clock signals supplied into the integrated circuits (hereinafter referred to as internal clocks), and as the operating speed of the integrated circuits is increased, the possibility of occurrence of malfunction due to the phase delay of the internal clocks with respect to reference clocks is increased. In such a condition, a PLL (Phase Locked Loop) circuit, a DLL (Delay Locked Loop) circuit have been broadly used to synchronize the reference clocks and the internal clocks in phase. Particularly, the DLL circuit adjusts the phase through digital processing, and thus it has an advantage that it has higher resistance to noises occurring in surrounding circuits than the PLL circuit which adjusts the phase in an analog style by using a voltage control oscillator or the like, and it can be easily designed.
FIG. 1 is a block diagram showing a DLL circuit described in Japanese Laid-open Patent Publication No. Hei-10-270998.
The conventional DLL circuit 81 comprises phase comparator 82 for comparing the phase of reference clock RCLK with the phase of feedback clock FBCLK and outputting phase comparison result PCOMP, variable delaying portion 83 for increasing/reducing the delay amount of the reference clock RCLK on the basis of control signal CONT and outputting the delay-increased/reduced clock as output clock OCLK, and controller 84 for generating and outputting the control signal CONT on the basis of the phase comparison result PCOMP. The output clock OCLK is input to clock supply buffer 85, and the output of the clock supply buffer 85 is supplied into an internal circuit (not shown) as an internal clock, and also input into the phase comparator 82 as the feedback clock FBCLK.
FIG. 2A is a circuit diagram showing the phase comparator 82.
The phase comparator 82 comprises flip flop (hereinafter referred to as xe2x80x9cFFxe2x80x9d) 91, and it reads out the feedback clock FBCLK in synchronism with the rise-up of the reference clock RCLK, and outputs the phase comparison result PCOMP. As shown in a phase-advance/phase-delay judging diagram of FIG. 2B, the controller 84 judges that the feedback clock FBCLK is under a phase-advanced state with respect to the reference clock RCLK if the phase judgment result PCOMP is equal to logic xe2x80x9c1xe2x80x9d, and increases the delay amount of a variable delay portion 83 at the next clock time to delay the phase of the output clock OCLK. Likewise, if the phase judgment result PCOMP is equal to logic xe2x80x9c0xe2x80x9d, the controller 84 judges that the feedback clock FBCLK is under a phase-delayed state with respect to the reference clock RCLK , and reduces the delay amount of the variable delay portion 83 at the next clock time to advance the phase of the output clock OCLK. By adjusting the phase as described above, the DLL circuit 81 can synchronize the phase of the feedback clock FBCLK (this clock is also a clock to be input into an integrated circuit) with the phase of the reference clock RCLK. Under the phase synchronized state, the phase comparison result PCOMP repetitively takes each of logic xe2x80x9c1xe2x80x9d and logic xe2x80x9c0xe2x80x9d.
However, in the conventional DLL circuit described above, there occurs a faked synchronization state in which the phase synchronizing operation is stagnant under the state that the rise-up of the reference clock RCLK is coincident with the falling of the feedback clock FBCLK, and this faked synchronization state may disturb quick shift to a normal phase synchronized state.
FIG. 2C is an operation timing chart under the faked synchronized state.
In a case where the phase comparison result PCOMP is varied from the logic xe2x80x9c1xe2x80x9d to the logic xe2x80x9c0xe2x80x9d (or from the logic xe2x80x9c0xe2x80x9d to the logic xe2x80x9c1xe2x80x9d) due to some factor (occurrence of jitter in the reference clock or the like) when the rise-up of the reference clock RCLK is substantially coincident with the falling of the feedback clock FBCLK, the phase comparison result PCOMP is repetitively and alternately switched between the logic xe2x80x9c1xe2x80x9d and the logic xe2x80x9c0xe2x80x9d as shown in FIG. 2C because there is a time delay between the phase comparison operation and the delay amount control operation, so that there occurs a faked synchronized state in which the phase synchronizing operation is stagnant under the state that the reference clock RCLK and the feedback clock FBCLK keep a phase difference of 180 degrees.
An object of the present invention is to provide a DLL circuit that can prevent occurrence of such a faked synchronization state, and implement a normal synchronization state stably and quickly.
In according with a first aspect of the present invention is provided a DLL circuit comprising: an edge detecting/phase comparing portion for receiving a first clock and a second clock, comparing the rise-up variations of the first and second clocks or the falling variations thereof every period of the first clock, internally generating an original comparison signal which is set to a first logical level when the variation of the second clock is prior to the variation of the first clock and is set to a second logical level when the variation of the second clock is subsequent to the variation of the first clock, and outputting the original comparison signal as a subsequent phase comparison result signal when it is detected that the level of the first clock and the level of the second clock have been varied in the same direction within a predetermined time, while keeping the output logical level of the phase comparison result signal and outputting the phase comparison result signal as a subsequent phase comparison result signal when it is detected that the level of the first clock and the level of the second clock have been varied in the opposite directions within the predetermined time; a variable delay portion for receiving the first clock, delaying the first clock on the basis of a control signal and outputting the delayed first clock as an output clock; and a controller for outputting the control signal which instructs the variable delay portion to increase the delay amount when the phase comparison result signal is set to the first logical level, and also instructs the variable delay portion to reduce the delay amount when the phase comparison result signal is set to the second logical level.
In according with a second aspect of the present invention is provided a DLL circuit comprising: a frequency multiplier for receiving a first clock and multiplying the frequency of the first clock to generate and output a frequency-multiplied clock; an edge detecting/phase comparing portion for receiving the first clock and the second clock, comparing the rise-up variations of the first and second clocks or the falling variations thereof every period of the first clock, internally generating an original comparison signal which is set to a first logical level when the variation of the second clock is prior to the variation of the first clock and is set to a second logical level when the variation of the second clock is subsequent to the variation of the first clock, and outputting the original comparison signal as a subsequent phase comparison result signal when it is detected that the level of the first clock and the level of the second clock have been varied in the same direction within a predetermined time, while keeping the output logical level of the phase comparison result signal and then outputting the phase comparison result signal as a subsequent phase comparison result signal when it is detected that the level of the first clock and the level of the second clock have been varied in the opposite directions within the predetermined time; a variable delay portion for receiving the frequency-multiplied clock, delaying the frequency-multiplied clock on the: basis of a control signal and outputting the delayed frequency-multiplied clock as an output clock; and a controller for outputting the control signal which instructs the variable delay portion to increase the delay amount when the phase comparison result signal is set to the first logical level, and also instructs the variable delay portion to reduce the delay amount when the phase comparison result signal is set to the second logical level.
In according with a third aspect of the present invention is provided a DLL circuit comprising: an edge detecting/phase comparing portion for receiving a first clock and a second clock, comparing the rise-up variations of the first and second clocks or the falling variations thereof every period of the first clock, outputting a phase comparison result signal which is set to a first logical level when the variation of the second clock is prior to the variation of the first clock and to a second logical level when the variation of the second clock is subsequent to the variation of the first clock, and outputting a phase selecting signal whose logical level is inverted every time it is detected that the level of the first clock and the level of the second clock have been varied in the opposite directions within a predetermined time; an input phase selecting circuit portion for receiving the first clock, generating an inverted signal, selecting the first clock and outputting it as a selected clock when the phase selecting signal is set to a predetermined logical level, while selecting an inverted signal of the first clock and then outputting the inverted signal as the selected clock when the phase selection signal has an inverted level of a predetermined logic level; a variable delay portion for receiving the selected clock, delaying the selected clock on the basis of a control signal and outputting the delayed selected clock,as an output clock; and a controller for outputting the control signal which instructs the variable delay portion to increase the delay amount when the phase comparison result signal is set to the first logical level, and also instructs the variable delay portion to reduce the delay amount when the phase comparison result signal is set to the second logical level.